// *************************************************************************
// IVe-NOTE : REQUIRED : Design top file : 07 Example - DUT
// -------------------------------------------------------------------------
// Use this section to define an example DUT for your UVe.
// To do so replace the following DUT skeleton with an actual DUT.
// If you choose to replace this file, or rename it, you should update the
// example config file and demo file accordingly.

// Environment constants
`define AHB_DATA_WIDTH          32              // AHB bus data width 
`define AHB_ADDR_WIDTH          32              // AHB bus address width 
`define AHB_DATA_MAX_BIT        31              // MUST BE: AHB_DATA_WIDTH - 1
`define AHB_ADDRESS_MAX_BIT     31              // MUST BE: AHB_ADDR_WIDTH - 1


`define DEFAULT_HWDATA_VALUE    {`AHB_DATA_WIDTH{1'b0}} // All zeros
`define DEFAULT_HADDR_VALUE     {`AHB_ADDR_WIDTH{1'b0}} // All zeros
`define DEFAULT_HTRANS_VALUE    2'b00                  // IDLE
`define DEFAULT_HWRITE_VALUE    1'b0                    // READ
`define DEFAULT_HBURST_VALUE    3'b000                  // SINGLE
`define DEFAULT_HSIZE_VALUE     3'b010                  // WORD
`define DEFAULT_HPROT_VALUE     4'b0011                 // NON_CACHE, NON_BUFFERABLE, PRIVALIGED, DATA
`define DEFAULT_HLOCK_VALUE     1'b0                    // MASTER IS NOT LOCKING

`define DEFAULT_HREADY_VALUE     1'b1                  
`define DEFAULT_HRESP_VALUE     1'b0                 
`define DEFAULT_HRDATA_VALUE     {`AHB_DATA_WIDTH{1'b0}}                    // MASTER IS NOT LOCKING


module vv_ahblite_skeleton;

   reg reset_n;	
   reg clock;
   //---------------------------------
   //master bus signals
   //---------------------------------
   wire [`AHB_ADDRESS_MAX_BIT:0]  h_addr;
   wire	        h_write;
   wire [2:0]   h_size;
   wire [2:0]   h_burst;
   wire [3:0]   h_prot;
   wire [1:0]   h_trans;
   wire         h_mastlock;
   wire [`AHB_DATA_MAX_BIT:0]  h_wdata;
   
   //------------------------------
   //slave signals
   //------------------------------
   //---------------------------
   // post-mux 
   wire         h_ready;
   wire         h_resp;
   wire [`AHB_DATA_MAX_BIT:0] h_rdata;
   
   // HSELx signals
   wire			h_sel_s0;
   wire			h_sel_s1;
   wire			h_sel_s2;
   wire			h_sel_s3;
   
   
   wire         h_readyout_S0;
   wire         h_resp_S0;
   wire [`AHB_DATA_MAX_BIT:0] h_rdata_S0;
   
   wire         h_readyout_S1;
   wire         h_resp_S1;
   wire [`AHB_DATA_MAX_BIT:0] h_rdata_S1;
   
   wire         h_readyout_S2;
   wire         h_resp_S2;
   wire [`AHB_DATA_MAX_BIT:0] h_rdata_S2;
   
   wire         h_readyout_S3;
   wire         h_resp_S3;
   wire [`AHB_DATA_MAX_BIT:0] h_rdata_S3;  
   //////////////////
   

  
   
   vv_ahblite_mux  vv_ahblite_mux(//output
        .hready(h_ready),
        .hresp(h_resp),
        .hrdata(h_rdata),
        
         //input
        .hready0(h_readyout_S0), 
        .hready1(h_readyout_S1),
        .hready2(h_readyout_S2),
        .hready3(h_readyout_S3),

        .hresp0(h_resp_S0),
        .hresp1(h_resp_S1),
        .hresp2(h_resp_S2),
        .hresp3(h_resp_S3),

        .hrdata0(h_rdata_S0),
        .hrdata1(h_rdata_S1),
        .hrdata2(h_rdata_S2),
        .hrdata3(h_rdata_S3),

        .hsel0(h_sel_s0),
        .hsel1(h_sel_s1),
        .hsel2(h_sel_s2),
        .hsel3(h_sel_s3),
        .clock(clock),
        .reset_n(reset_n)
        );
   
   
   initial clock = 1'b1;
   always #50 clock <= ~clock;
   
   initial
   	begin
   	// initialisation
//   		h_sel_s0 = 1'b0;
//        h_sel_s1 = 1'b0;
//        h_sel_s2 = 1'b0;
//        h_sel_s3 = 1'b0;
//         
//         
//        h_wdata = `DEFAULT_HWDATA_VALUE;
//        h_addr  = `DEFAULT_HADDR_VALUE;
//        h_trans = `DEFAULT_HTRANS_VALUE;
//        h_write = `DEFAULT_HWRITE_VALUE;
//        h_burst = `DEFAULT_HBURST_VALUE;
//        h_size  = `DEFAULT_HSIZE_VALUE;
//        h_prot  = `DEFAULT_HPROT_VALUE;
//         
//          // s0
//        h_readyout_S0  = 1'b1;
//        h_resp_S0   = 1'b1;;
//        h_rdata_S0  = 32'h00000000;
//
//
//         // s1
//        h_readyout_S1  = 1'b1;
//        h_resp_S1   =1'b1;
//        h_rdata_S1  = 32'h00000000;
//
//         // s2
//        h_readyout_S2  = 1'b1;
//        h_resp_S2   = 1'b1;
//        h_rdata_S2  = 32'h00000000;
//
//         // s3
//        h_readyout_S3  = 1'b1;
//        h_resp_S3   =1'b1;
//        h_rdata_S3 = 32'h00000000;
         
         
   	// reset init
	   reset_n = 1;
	   #50;
	   reset_n = 0;
	   #550;
	   reset_n = 1;
   end
   
   // get VCD
   initial
    begin
       $dumpvars;
    end
   
endmodule

// *************************************************************************


